Pour démarrer rapidement et ne pas lire toute la suite :

La rapidité de l'exécution pourra être contrôlée en utilisant les flèches (<< pour ralentir et >> pour accélérer)

Plus de détails

The simulation has a main "B" bus that interconnects all the components and a smaller "A" bus (on the left) that connects the registers to the ALU (Arithmetic and Logic Unit). There is a hidden bus that connects the registers (and the flags register) and none of the control logic is shown. You have to imagine the Control Unit having wires connecting to and controlling all the other components.

The flags register holds the result of the last ALU operation - negative (N), zero (Z), carry (C) and overflow (V). Overflow means overflow for a 2's complement operation whereas Carry means overflow for the same operation seen as an unsigned operation. For the shift operations Carry holds the last bit shifted out and for subtract Carry is "not borrow" (so it is the equivalent of negating the second number and adding). Instructions which do not use the ALU do not alter the flags and neither do address calculations (ADD and SUB to SP). You have to imagine links from the ALU to the flag bits and from the flag bits to the Control Unit (so the conditional branches can be executed).

Almost everything is based on 16 bit words. The Assembler shows signed (2's complement) in memory by default but there is an option to show memory and Registers 0-7 in unsigned or hex (and memory in binary). Output to device 4 is treated as signed but you can output unsigned (device 5), hex (device 6) or character (device 7). You can input hex as 0xnnnn everywhere a number is expected.

As well as inputting a program into the Assembly Language area you can input numbers into the Program Counter and directly into memory. When you Submit the Assembly Language a memory clear and a reset are done and the program is assembled into memory.

There is an instruction list and some other notes at www.peterhigginson.co.uk/RISC/instruction_set.pdf. The instruction set is loosely based on the ARM 16bit instruction set but with some optimisations for the smaller address range. E.g. ARM has no direct conditional branches (they are all relative) and does not have a direct ADD and SUB.

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There is a discussion of design choices and more information about the implementation at www.peterhigginson.co.uk/RISC/RISC_simulator_design.pdf.

When running, you can use << and >> to slow down or speed up the execution. Speeds of 6 and over do not show the moving blobs. If you increase from 5, it has to finish the current instruction before switching speeds. If you just want to develop code, the "fast" and "execute" options do not show the moving blobs. (Fast is the fastest speed and execute is the slowest speed without the moving blobs.) "Stop" pauses the moving blobs and a second click completes the current instruction.

RISC Simulator in JavaScript

© 2016 Peter L Higginson (plh256 at hotmail.com)

I am debugging this using Chrome so if you get any problems please check whether they appear in Chrome as well. (I would still be interested to hear about browser specific issues and any use made of the project.)

The LMC simulator is at www.peterhigginson.co.uk/LMC.

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